High-voltage metal-oxide-semiconductor (HVMOS) devices are widely used in many electrical devices, such as input/output (I/O) circuits, CPU power supplies, power management systems, AC/DC converters, etc. HVMOS devices typically include drain regions and laterally-diffused drain regions enclosing drain regions. Laterally-diffused drain regions are typically well regions having lower doping concentrations than the drain regions, thus having high breakdown electrical fields.
FIG. 1 illustrates a conventional HVNMOS device 2, which includes gate oxide 10, gate electrode 12 on gate oxide 10, drain region 6 in n-well region 4, and source region 8 in p-well region 7. Shallow trench isolation (STI) region 14 spaces drain region 6 apart from gate electrode 12 so that a high drain-to-gate voltage can be applied.
It is known that high electrical fields are typically generated at interface regions. For HVNMOS device 2, when a high voltage is applied between drain region 6 and source region 8, a high electrical field is generated at a region proximate p-n junction 16, which becomes the weak point of the HVNMOS device 2. The generation of the high electrical field causes the reduction in breakdown voltage of HVNMOS device 2. This problem worsens when the device dimensions become smaller, and thus the electrical fields become higher.
Novel methods for reducing electrical fields at p-n junctions are thus needed to improve breakdown voltages of high-voltage MOS devices.